The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2010

Filed:

Sep. 19, 2007
Applicants:

Kenneth Ferguson, Edinburgh, GB;

Kenneth Mackie, Edinburgh, GB;

Gilles S. C. Lamant, Sunnyvale, CA (US);

Sravasti Gupta Nair, Fremont, CA (US);

Inventors:

Kenneth Ferguson, Edinburgh, GB;

Kenneth Mackie, Edinburgh, GB;

Gilles S. C. Lamant, Sunnyvale, CA (US);

Sravasti Gupta Nair, Fremont, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment a new method to address configuring a logical design and libraries of design elements with additional information is proposed that may be used to create a physical design from that logical design. Logical designs may be generic, while physical design libraries are normally targeted towards specific technology. Consequently, there can be a mapping from the cells in a logical library to cells which correspond to their implementation in a physical library. In one embodiment, annotations required to map from logical design to physical design may be stored in a separate design view. In one embodiment the user can modify the physical mapping attributes of cells, instances, and occurrences in the logical design and save the modifications back to the physical configuration view.


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