The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Mar. 31, 2006
Applicants:
John R. Cherukuri, Folsom, CA (US);
AK R. Ahmed, Rancho Condova, CA (US);
Arun Subbiah, Folsom, CA (US);
Satish Damaraju, El Dorado Hills, CA (US);
Inventors:
John R. Cherukuri, Folsom, CA (US);
Ak R. Ahmed, Rancho Condova, CA (US);
Arun Subbiah, Folsom, CA (US);
Satish Damaraju, El Dorado Hills, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract
Provided herein are schemes for reducing leakage in dynamic circuits during sleep modes.
Cherukuri, John. (2010). Circuit technique to reduce leakage during reduced power mode (U.S. Patent No. 7805619). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7805619
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile