The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
May. 04, 2009
Chin-hsien Chen, Hsinchu, TW;
Ying-tso Chen, Hsinchu, TW;
Chien-hung Liu, Hsinchu, TW;
Shou-wei Huang, Hsinchu, TW;
Chin-Hsien Chen, Hsinchu, TW;
Ying-Tso Chen, Hsinchu, TW;
Chien-Hung Liu, Hsinchu, TW;
Shou-Wei Huang, Hsinchu, TW;
MACRONIX International Co., Ltd, Hsinchu, TW;
Abstract
A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.