The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2010

Filed:

Oct. 17, 2008
Applicants:

Kai-ling Chiu, Pingtung County, TW;

Chih-yu Tseng, Hsinchu, TW;

Victor-chiang Liang, Hsin-Chu, TW;

You-ren Liu, Kaohsiung, TW;

Chih-chen Hsueh, Kaohsiung, TW;

Inventors:

Kai-Ling Chiu, Pingtung County, TW;

Chih-Yu Tseng, Hsinchu, TW;

Victor-Chiang Liang, Hsin-Chu, TW;

You-Ren Liu, Kaohsiung, TW;

Chih-Chen Hsueh, Kaohsiung, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.


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