The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2010

Filed:

Feb. 23, 2007
Applicants:

Romain Wacquez, Grenoble, FR;

Philippe Coronel, Barraux, FR;

Jessy Bustos, Le Touvet, FR;

Inventors:

Romain Wacquez, Grenoble, FR;

Philippe Coronel, Barraux, FR;

Jessy Bustos, Le Touvet, FR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/335 (2006.01);
U.S. Cl.
CPC ...
Abstract

Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.


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