The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Jan. 25, 2008
Venkatesh P. Gopinath, Fremont, CA (US);
Krishnan Sundaresan, Sunnyvale, CA (US);
Jaewon OH, Cupertino, CA (US);
KE Peng, Fremont, CA (US);
Robert E. Mains, Morgan Hill, CA (US);
Venkatesh P. Gopinath, Fremont, CA (US);
Krishnan Sundaresan, Sunnyvale, CA (US);
Jaewon Oh, Cupertino, CA (US);
Ke Peng, Fremont, CA (US);
Robert E. Mains, Morgan Hill, CA (US);
Oracle America, Inc., Redwood City, CA (US);
Abstract
Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.