The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Nov. 16, 2007
Applicants:

Sung-young Lee, Gyeonggi-do, KR;

Sung-min Kim, Incheon-si, KR;

Dong-gun Park, Gyeonggi-do, KR;

Chang-woo OH, Gyeonggi-do, KR;

Eun-jung Yun, Seoul, KR;

Inventors:

Sung-Young Lee, Gyeonggi-do, KR;

Sung-Min Kim, Incheon-si, KR;

Dong-Gun Park, Gyeonggi-do, KR;

Chang-Woo Oh, Gyeonggi-do, KR;

Eun-Jung Yun, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.


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