The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Jan. 30, 2008
Thomas J. Kropewnicki, Austin, TX (US);
Ritwik Chatterjee, Austin, TX (US);
Kurt H. Junker, Austin, TX (US);
Thomas J. Kropewnicki, Austin, TX (US);
Ritwik Chatterjee, Austin, TX (US);
Kurt H. Junker, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.