The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Jul. 15, 2008
Applicants:

Satoshi Shiraki, Toyohashi, JP;

Yoshiaki Nakayama, Okazaki, JP;

Shoji Mizuno, Okazaki, JP;

Takashi Nakano, Nukata-gun, JP;

Akira Yamada, Nukata-gun, JP;

Inventors:

Satoshi Shiraki, Toyohashi, JP;

Yoshiaki Nakayama, Okazaki, JP;

Shoji Mizuno, Okazaki, JP;

Takashi Nakano, Nukata-gun, JP;

Akira Yamada, Nukata-gun, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.


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