The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Jun. 04, 2009
Sun-ghil Lee, Seongnam-si, KR;
Young-pil Kim, Suwon-si, KR;
Yu-gyun Shin, Seongnam-si, KR;
Jong-wook Lee, Yongin-si, KR;
Young-eun Lee, Goyang-si, KR;
Sun-Ghil Lee, Seongnam-si, KR;
Young-Pil Kim, Suwon-si, KR;
Yu-Gyun Shin, Seongnam-si, KR;
Jong-Wook Lee, Yongin-si, KR;
Young-Eun Lee, Goyang-si, KR;
Abstract
A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.