The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7799642 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 21, 2010

Filed:

Oct. 02, 2007
Applicants:

Shih Tzung Su, Shulin, TW;

Jun Zeng, Torrance, CA (US);

Poi Sun, Torrance, CA (US);

Kao Way Tu, Jhonghe, TW;

Tai Chiang Chen, TianJin, CN;

Long LV, TianJin, CN;

Xin Wang, TianJin, CN;

Inventors:

Shih Tzung Su, Shulin, TW;

Jun Zeng, Torrance, CA (US);

Poi Sun, Torrance, CA (US);

Kao Way Tu, Jhonghe, TW;

Tai Chiang Chen, TianJin, CN;

Long Lv, TianJin, CN;

Xin Wang, TianJin, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.


Find Patent Forward Citations

Su, Shih. (2010). Trench mosfet and method of manufacture utilizing two masks (U.S. Patent No. 7799642). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7799642

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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