The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Dec. 29, 2003
Per H. Hammarlund, Hillsboro, OR (US);
Stephan J. Jourdan, Portland, OR (US);
Pierre Michaud, Bruz, FR;
Alexandre J. Farcy, Hillsboro, OR (US);
Morris Marden, Hillsboro, OR (US);
Robert L. Hinton, Hillsboro, OR (US);
Douglas M. Carmean, Beaverton, OR (US);
Per H. Hammarlund, Hillsboro, OR (US);
Stephan J. Jourdan, Portland, OR (US);
Pierre Michaud, Bruz, FR;
Alexandre J. Farcy, Hillsboro, OR (US);
Morris Marden, Hillsboro, OR (US);
Robert L. Hinton, Hillsboro, OR (US);
Douglas M. Carmean, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.