The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Oct. 02, 2008
Gordon Chiu, Richmond Hill, CA;
Deshanand Singh, Mississauga, CA;
Valavan Manohararajah, Scarborough, CA;
Stephen Brown, Toronto, CA;
Gordon Chiu, Richmond Hill, CA;
Deshanand Singh, Mississauga, CA;
Valavan Manohararajah, Scarborough, CA;
Stephen Brown, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
Systems and methods are provided for mapping logic functions from logic elements ('LEs') into synchronous embedded memory blocks ('EMBs') of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.