The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Dec. 06, 2007
Hui Xu, Menlo Park, CA (US);
Vinay Verma, San Jose, CA (US);
Anirban Rahut, Santa Clara, CA (US);
Jason H. Anderson, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Hui Xu, Menlo Park, CA (US);
Vinay Verma, San Jose, CA (US);
Anirban Rahut, Santa Clara, CA (US);
Jason H. Anderson, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.