The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Jul. 17, 2008
Michael D. Monkowski, New Windsor, NY (US);
Patricia A. O'neil, Newburgh, NY (US);
Michael D. Monkowski, New Windsor, NY (US);
Patricia A. O'Neil, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.