The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2010

Filed:

May. 21, 2009
Applicants:

Rohit Kapur, Cupertino, CA (US);

Tom W. Williams, Boulder, CO (US);

Cyrus Hay, Palo Alto, CA (US);

Inventors:

Rohit Kapur, Cupertino, CA (US);

Tom W. Williams, Boulder, CO (US);

Cyrus Hay, Palo Alto, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/30 (2006.01); G01R 31/26 (2006.01); G11B 20/20 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.


Find Patent Forward Citations

Loading…