The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Jun. 23, 2008
Kaushik DE, Bangalore, IN;
Eduard Cerny, Worcester, MA (US);
Pallab Dasgupta, Kharagpur, IN;
Bhaskar Pal, Bangalore, IN;
Partha Pratim Chakrabarti, Kharagpur, IN;
Kaushik De, Bangalore, IN;
Eduard Cerny, Worcester, MA (US);
Pallab Dasgupta, Kharagpur, IN;
Bhaskar Pal, Bangalore, IN;
Partha Pratim Chakrabarti, Kharagpur, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.