The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Apr. 29, 2008
Won-joo Kim, Hwaseong-si, KR;
Yoon-dong Park, Yongin-si, KR;
June-mo Koo, Seoul, KR;
Suk-pil Kim, Yongin-si, KR;
Tae-eung Yoon, Seoul, KR;
Tae-hee Lee, Yongin-si, KR;
Won-joo Kim, Hwaseong-si, KR;
Yoon-dong Park, Yongin-si, KR;
June-mo Koo, Seoul, KR;
Suk-pil Kim, Yongin-si, KR;
Tae-eung Yoon, Seoul, KR;
Tae-hee Lee, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.