The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Dec. 29, 2008
Ker-min Chen, Hsin-Chu, TW;
Ching-hao Shaw, San Jose, CA (US);
Ker-Min Chen, Hsin-Chu, TW;
Ching-Hao Shaw, San Jose, CA (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.