The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2010

Filed:

Jan. 30, 2006
Applicants:

Miho Nakamura, Yokohama, JP;

Yoshiyuki Fukuda, Ayase, JP;

Inventors:

Miho Nakamura, Yokohama, JP;

Yoshiyuki Fukuda, Ayase, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A ceramic wiring boardincludes a ceramic substrateand a wiring layerformed on the ceramic substrate. The wiring layerincludes a wiring partand a connection part, the wiring parthaving a base metal layer, a first diffusion preventive layerand a first Au layerwhich are stacked in sequence on a surface of the ceramic substrate, and the connection parthaving a second diffusion preventive layer, a void suppression layerand a solder layerwhich are stacked in sequence at a desired position on the wiring part. The void suppression layeris made of, for example, Au or an Au—Sn alloy containing 85 mass % or more of Au.


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Nakamura, Miho. (2010). Ceramic wiring board and process for producing the same, and semiconductor device using the same (U.S. Patent No. 7795732). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7795732

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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