The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2010

Filed:

Jan. 04, 2007
Applicants:

Steven Leibiger, Falmouth, ME (US);

Gary Dolny, Mountain Top, PA (US);

Inventors:

Steven Leibiger, Falmouth, ME (US);

Gary Dolny, Mountain Top, PA (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors. When the device is in an on state, current flows between the source and drain regions through the second region of the second conductivity type; and, when the device is in an off/blocking state, the second conductivity region is depleted four ways into the first and third regions of the stack and into the first and second trench capacitors.


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