The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Oct. 30, 2007
Philip Hui-yuh Tai, Cupertino, CA (US);
Yi-min Jiang, San Jose, CA (US);
Sung-hoon Kwon, Sunnyvale, CA (US);
Philip Hui-Yuh Tai, Cupertino, CA (US);
Yi-Min Jiang, San Jose, CA (US);
Sung-Hoon Kwon, Sunnyvale, CA (US);
SYNOPSYS, Inc., Mountain View, CA (US);
Abstract
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector 'I' and conductance matrix 'G' are used to solve for voltage drop ΔV, in a matrix equation GΔV=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.