The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Mar. 24, 2008
Peter Rabkin, Cupertino, CA (US);
Zhiyuan Wu, Sunnyvale, CA (US);
Min-hsing Peter Chen, Campbell, CA (US);
Jane W. Sowards, Fremont, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Min-fang Ho, Monte Sereno, CA (US);
Peter Rabkin, Cupertino, CA (US);
Zhiyuan Wu, Sunnyvale, CA (US);
Min-Hsing Peter Chen, Campbell, CA (US);
Jane W. Sowards, Fremont, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Min-Fang Ho, Monte Sereno, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.