The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2010

Filed:

Apr. 05, 2007
Applicants:

Gary D. Grise, Colchester, VT (US);

David J. Hathaway, Underhill, VT (US);

Vikram Iyengar, S. Burlington, VT (US);

Inventors:

Gary D. Grise, Colchester, VT (US);

David J. Hathaway, Underhill, VT (US);

Vikram Iyengar, S. Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as 'exercised.' Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.


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