Hardware managed context sensitive interrupt priority level control

Abstract

A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit () that multiplexes () a plurality of interrupt priority registers () based on the current context of the system that is identified in mode control selector (). By using the mode control selector () to selectively couple different priority level assignments to a priority encoding module (), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal () which will cause an interrupt to occur in the data processing system.