The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2010

Filed:

Jul. 10, 2007
Applicants:

Daisaku Ikoma, Osaka, JP;

Kyoji Yamashita, Osaka, JP;

Yasuyuki Sahara, Osaka, JP;

Katsuhiro Ootani, Osaka, JP;

Tomoyuki Ishizu, Osaka, JP;

Inventors:

Daisaku Ikoma, Osaka, JP;

Kyoji Yamashita, Osaka, JP;

Yasuyuki Sahara, Osaka, JP;

Katsuhiro Ootani, Osaka, JP;

Tomoyuki Ishizu, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.


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