The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Jun. 28, 2007
Kanji Otsuka, Higashiyamato-shi, Tokyo 207-0002, JP;
Tamotsu Usami, Kokubunji-shi, Tokyo 185-0035, JP;
Yutaka Akiyama, Hachiouji-shi, Tokyo 192-0914, JP;
Tsuneo Ito, Oume-shi, Tokyo 198-0171, JP;
Yuko Tanba, Oume-shi, Tokyo 198-0024, JP;
Kanji Otsuka, Higashiyamato-shi, Tokyo 207-0002, JP;
Tamotsu Usami, Kokubunji-shi, Tokyo 185-0035, JP;
Yutaka Akiyama, Hachiouji-shi, Tokyo 192-0914, JP;
Tsuneo Ito, Oume-shi, Tokyo 198-0171, JP;
Yuko Tanba, Oume-shi, Tokyo 198-0024, JP;
Other;
Fujitsu Microelectronics Limited, Yokohama, JP;
OKI Semiconductor Co., Ltd., Tokyo, JP;
Kyocera Corporation, Kyoto, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Fuji Xerox Co., Ltd., Tokyo, JP;
Renesas Technology Corp, Tokyo, JP;
Abstract
Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.