The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Dec. 21, 2007
Katherina E. Babich, Chappaqua, NY (US);
Bruce B. Doris, Brewster, NY (US);
David R. Medeiros, Ossining, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Katherina E. Babich, Chappaqua, NY (US);
Bruce B. Doris, Brewster, NY (US);
David R. Medeiros, Ossining, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.