The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2010
Filed:
Nov. 08, 2007
Hua Xue, Saratoga, CA (US);
Bertrand Leigh, Portland, OR (US);
Ju Shen, San Jose, CA (US);
Chris West, Portland, OR (US);
Mike Ray, Portland, OR (US);
Hua Xue, Saratoga, CA (US);
Bertrand Leigh, Portland, OR (US);
Ju Shen, San Jose, CA (US);
Chris West, Portland, OR (US);
Mike Ray, Portland, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.