The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2010

Filed:

Mar. 17, 2003
Applicants:

Jawahar Jain, Santa Clara, CA (US);

Subramanian K. Iyer, Austin, TX (US);

Amit Narayan, Redwood City, CA (US);

Debashis Sahoo, Stanford, CA (US);

Inventors:

Jawahar Jain, Santa Clara, CA (US);

Subramanian K. Iyer, Austin, TX (US);

Amit Narayan, Redwood City, CA (US);

Debashis Sahoo, Stanford, CA (US);

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for evaluating an erroneous state associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are executed using the information in order to identify an erroneous state associated with a sub-space within the target circuit. A path associated with the erroneous state is identified. The path reflects a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered.


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