The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2010
Filed:
Dec. 02, 2008
Michio Horiuchi, Nagano, JP;
Yasue Tokutake, Nagano, JP;
Shigeaki Suganuma, Nagano, JP;
Naoyuki Koizumi, Nagano, JP;
Fumimasa Katagiri, Nagano, JP;
Michio Horiuchi, Nagano, JP;
Yasue Tokutake, Nagano, JP;
Shigeaki Suganuma, Nagano, JP;
Naoyuki Koizumi, Nagano, JP;
Fumimasa Katagiri, Nagano, JP;
Shinko Electric Industries Co., Ltd, Nagano-shi, Nagano, JP;
Abstract
A multilayer wiring board includes: a substrate; connection pads arranged in a square grid fashion; and wiring patterns. Relationship between the connection pads and the wiring patterns satisfies: {(Ndl+1)P−d−s}/(w+s)>2Ndr+Ndl(a+1)+2, wherein P is a pitch of the connection pads, d is a diameter of the connection pads, s is a minimum interval between the wiring patterns and is a minimum interval between the wiring pattern and the connection pad that are adjacent to each other, w is a minimum width of the wiring patterns, Ndl is the number of non-pad rows in each of the non-pad regions, Ndr is the number of non-pad columns in each of non-pad region, and a is an integer of (P−d−s)/(w+s).