Semiconductor memory integrated circuit and its manufacturing method

Abstract

A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film () in the cell array region, gate oxide film () for a high-voltage circuit and gate oxide film () for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (). After that, device isolation grooves () are formed and buried with a device isolation insulating film (). The first-layer polycrystalline silicon film () is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film () is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film () and the second-layer polycrystalline silicon film (). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film (), second-layer polycrystalline silicon film () and third-layer polycrystalline silicon film, and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.