The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2010

Filed:

Jun. 25, 2009
Applicant:

Kyoung Bong Rouh, Icheon-si, KR;

Inventor:

Kyoung Bong Rouh, Icheon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.


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