The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2010
Filed:
May. 08, 2006
Kyoko Izuha, Yokohama, JP;
Fumihiro Minami, Yokohama, JP;
Toshiaki Ueda, Yokohama, JP;
Ryuji Ogawa, Yokohama, JP;
Satoshi Tanaka, Kawasaki, JP;
Kyoko Izuha, Yokohama, JP;
Fumihiro Minami, Yokohama, JP;
Toshiaki Ueda, Yokohama, JP;
Ryuji Ogawa, Yokohama, JP;
Satoshi Tanaka, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.