The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2010
Filed:
May. 15, 2008
Chad Allen Adams, Byron, MN (US);
Elizabeth Lair Gerhard, Rochester, MN (US);
Sharon Huertas Cesky, Rochester, MN (US);
Jeffrey Milton Scherer, Rochester, MN (US);
Chad Allen Adams, Byron, MN (US);
Elizabeth Lair Gerhard, Rochester, MN (US);
Sharon Huertas Cesky, Rochester, MN (US);
Jeffrey Milton Scherer, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.