The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2010
Filed:
Jul. 09, 2008
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Henry K. Utomo, Poughkeepsie, NY (US);
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Henry K. Utomo, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.