The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2010

Filed:

Jan. 06, 2009
Applicants:

Takeshi Kishi, Yokohama, JP;

Tetsuya Hattori, Yokohama, JP;

Kazunori Fujimoto, Yokohama, JP;

Inventors:

Takeshi Kishi, Yokohama, JP;

Tetsuya Hattori, Yokohama, JP;

Kazunori Fujimoto, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 43/12 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
Abstract

A process for the semiconductor laser diode is disclosed, which prevents the abnormal growth occurred at the second growth for the burying region of the buried hetero structure. The ICP (Induction-Coupled Plasma) CVD apparatus forms a silicon oxide file with a thickness of above 2 μm as adjusting the bias power P. Patterning the silicon oxide mask and dry-etching the semiconductor layers, a mesa structure including the active layer may be formed. As leaving the patterned silicon oxide film, the second growth for the burying region buries the mesa structure. The residual stress of the silicon oxide film is −250 to −150 MPa at a room temperature, while, it is −200 to 100 MPa at temperatures from 500 to 700° C.


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