The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Jan. 15, 2009
Simon Su-horng Lin, Hsinchu, TW;
Yu-ming Lee, Taichung, TW;
Shao-yen Ku, Jhubei, TW;
Chi-ming Yang, Hsian-San District, TW;
Chyi-shyuan Chern, Taipei, TW;
Chin-hsiang Lin, Hsin Chu, TW;
Simon Su-Horng Lin, Hsinchu, TW;
Yu-Ming Lee, Taichung, TW;
Shao-Yen Ku, Jhubei, TW;
Chi-Ming Yang, Hsian-San District, TW;
Chyi-Shyuan Chern, Taipei, TW;
Chin-Hsiang Lin, Hsin Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.