The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Aug. 14, 2008
Griselda Bonilla, Fishkill, NY (US);
Kaushik Chanda, Fishkill, NY (US);
Ronald G. Filippi, Wappingers Falls, NY (US);
Stephan Grunow, Poughkeepsie, NY (US);
Sujatha Sankaran, New Paltz, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Theodorus Eduardus Standaert, Pine Bush, NY (US);
Griselda Bonilla, Fishkill, NY (US);
Kaushik Chanda, Fishkill, NY (US);
Ronald G. Filippi, Wappingers Falls, NY (US);
Stephan Grunow, Poughkeepsie, NY (US);
Sujatha Sankaran, New Paltz, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Theodorus Eduardus Standaert, Pine Bush, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.