The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2010
Filed:
May. 15, 2009
Hwong-kwo Lin, Palo Alto, CA (US);
GE Yang, Pleasanton, CA (US);
Guoqing Ning, Santa Clara, CA (US);
Charles Chew-yuen Young, Cupertino, CA (US);
Hwong-Kwo Lin, Palo Alto, CA (US);
Ge Yang, Pleasanton, CA (US);
Guoqing Ning, Santa Clara, CA (US);
Charles Chew-Yuen Young, Cupertino, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from the high voltage domain to a low voltage domain, where VDD_IO is the supply voltage of the high voltage domain and VDD_Logic is the supply voltage of the low voltage domain. A level shifting circuit using a combination of I/O and logic transistors avoids exceeding a maximum tolerable voltage across the gate and source of any of the transistors. The level shifting circuit operates includes a reference voltage circuit that is independent of VDD_IO, so the same level shifting circuit may be used for various VDD_IO voltages. Additionally, the voltage level shifting circuit is not sensitive to scaling of VDD_Logic and operates properly when VDD_Logic is reduced due to shrinking silicon process technology and/or is reduced for a low power application.