The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2010

Filed:

Jun. 12, 2007
Applicants:

Yoji Nishio, Tokyo, JP;

Yutaka Uematsu, Tokyo, JP;

Seiji Funaba, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Tsutomu Hara, Tokyo, JP;

Koichiro Aoki, Tokyo, JP;

Inventors:

Yoji Nishio, Tokyo, JP;

Yutaka Uematsu, Tokyo, JP;

Seiji Funaba, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Tsutomu Hara, Tokyo, JP;

Koichiro Aoki, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor deviceincludes plural memory chipsstacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal Lis connected to data strobe signal (DQS) pad of first memory chip. Inverted data strobe signal line for /DQS signal Lis connected to inverted data strobe signal (/DQS) pad of second memory chip


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