The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Feb. 14, 2005
Tadahiro Kuroda, Yokohama, JP;
Daisuke Mizoguchi, Yokohama, JP;
Yusmeeraz Binti Yusof, Yokohama, JP;
Noriyuki Miura, Yokohama, JP;
Takayasu Sakurai, Tokyo, JP;
Tadahiro Kuroda, Yokohama, JP;
Daisuke Mizoguchi, Yokohama, JP;
Yusmeeraz Binti Yusof, Yokohama, JP;
Noriyuki Miura, Yokohama, JP;
Takayasu Sakurai, Tokyo, JP;
KEIO University, Tokyo, JP;
Abstract
An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13, 13, 13and the first through the third receiver coils 15, 15, 15are formed by wiring on the first through the third LSI chips 11, 11, 11. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12, 12, 12are connected to the first through the third transmitter coils 13, 13and 13, respectively, and the first through the third receiver circuits 14, 14, 14are connected to the first through the third receiver coils 15, 15, 15, respectively.