The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2010

Filed:

Mar. 09, 2006
Applicants:

Carl E. Larson, San Jose, CA (US);

Sharee J. Mcnab, Huntebury Christchurch, NZ;

Steven E. Steen, Peekskill, NY (US);

Raman G. Viswanathan, Briarcliff Manor, NY (US);

Gregory M. Wallraff, Morgan Hill, CA (US);

Inventors:

Carl E. Larson, San Jose, CA (US);

Sharee J. McNab, Huntebury Christchurch, NZ;

Steven E. Steen, Peekskill, NY (US);

Raman G. Viswanathan, Briarcliff Manor, NY (US);

Gregory M. Wallraff, Morgan Hill, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of lithography is disclosed, which allows for independent resist process optimization of two or more exposure steps that are performed on a single resist layer. By providing for a separate post-exposure bake after each resist exposure step, pattern resolution for each exposure can be optimized. The method can generally be used with different lithographic techniques, and is well-suited for hybrid lithography. It has been applied to the fabrication of a device, in which the active area and the gate levels are defined in separate mask levels using hybrid lithography with an e-beam source and a 248 nm source respectively. Conditions for post-exposure bakes after the two exposure steps are independently adjusted to provide for optimized results.


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