The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2010

Filed:

Feb. 16, 2008
Applicants:

Joseph E. Eckelman, Hopewell Junction, NY (US);

Kevin C. Gotze, Aloha, OR (US);

James A. Kyle, Germantown, NY (US);

Jennifer Yuk Sim Yan, Fishkill, NY (US);

Inventors:

Joseph E. Eckelman, Hopewell Junction, NY (US);

Kevin C. Gotze, Aloha, OR (US);

James A. Kyle, Germantown, NY (US);

Jennifer Yuk Sim Yan, Fishkill, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed. Test interrogations are distributed on-chip through an LSSD shift register chain to individually evaluate each of a plurality of the oscillators.


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