The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Aug. 13, 2007
Robert J. Allen, Jericho, VT (US);
Cam V. Endicott, Essex Junction, VT (US);
Fook-luen Heng, Yorktown Heights, NY (US);
Jason D. Hibbeler, Williston, VT (US);
Kevin W. Mccullen, Essex Junction, VT (US);
Rani Narayan, San Jose, CA (US);
Robert F. Walker, St. George, VT (US);
Xin Yuan, Essex Junction, VT (US);
Robert J. Allen, Jericho, VT (US);
Cam V. Endicott, Essex Junction, VT (US);
Fook-Luen Heng, Yorktown Heights, NY (US);
Jason D. Hibbeler, Williston, VT (US);
Kevin W. McCullen, Essex Junction, VT (US);
Rani Narayan, San Jose, CA (US);
Robert F. Walker, St. George, VT (US);
Xin Yuan, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet 'edge coverage' requirements.