The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
May. 07, 2008
Scott Barnett Swaney, Catskill, NY (US);
Kenneth Lundy Ward, Austin, TX (US);
Tobias Webel, Schwaebisch-Gmuend, DE;
Ulrich Weiss, Holzgerlingen, DE;
Matthias Woehrle, Boeblingen, GR;
Scott Barnett Swaney, Catskill, NY (US);
Kenneth Lundy Ward, Austin, TX (US);
Tobias Webel, Schwaebisch-Gmuend, DE;
Ulrich Weiss, Holzgerlingen, DE;
Matthias Woehrle, Boeblingen, GR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.