The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2010

Filed:

Jun. 30, 2004
Applicants:

Ashish V. Choubal, Austin, TX (US);

Madhu R. Gumma, Austin, TX (US);

Christopher T. Foulds, Austin, TX (US);

Mohannad M. Noah, Austin, TX (US);

Inventors:

Ashish V. Choubal, Austin, TX (US);

Madhu R. Gumma, Austin, TX (US);

Christopher T. Foulds, Austin, TX (US);

Mohannad M. Noah, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a method, system, and program for managing memory requests for logic blocks or clients of a device. In one embodiment, busses are separated by the type of data to be carried by the busses. In another aspect, data transfers are decoupled from the memory requests which initiate the data transfers. In another aspect, clients competing for busses are arbitrated and selected memory requests may be provided programmable higher priority than other memory operations of a similar type.


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