The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Oct. 22, 2008
Kazuyuki Sawada, Toyama, JP;
Yuji Harada, Hyogo, JP;
Masahiko Niwayama, Kyoto, JP;
Saichirou Kaneko, Kyoto, JP;
Yoshimi Shimizu, Osaka, JP;
Kazuyuki Sawada, Toyama, JP;
Yuji Harada, Hyogo, JP;
Masahiko Niwayama, Kyoto, JP;
Saichirou Kaneko, Kyoto, JP;
Yoshimi Shimizu, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.