The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2010
Filed:
Sep. 30, 2005
Bixia Zheng, Palo Alto, CA (US);
Cheng C. Wang, Cupertino, CA (US);
Ho-seop Kim, Cupertino, CA (US);
Mauricio Breternitz, Jr., Austin, TX (US);
Youfeng Wu, Palo Alto, CA (US);
Bixia Zheng, Palo Alto, CA (US);
Cheng C. Wang, Cupertino, CA (US);
Ho-seop Kim, Cupertino, CA (US);
Mauricio Breternitz, Jr., Austin, TX (US);
Youfeng Wu, Palo Alto, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.