The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2010

Filed:

Sep. 30, 2002
Applicants:

Sujat Jamil, Chandler, AZ (US);

Hang T. Nguyen, Tempe, AZ (US);

Samantha J. Edirisooriya, Tempe, AZ (US);

David E. Miner, Chandler, AZ (US);

R. Frank O'bleness, Tempe, AZ (US);

Steven J. Tu, Phoenix, AZ (US);

Inventors:

Sujat Jamil, Chandler, AZ (US);

Hang T. Nguyen, Tempe, AZ (US);

Samantha J. Edirisooriya, Tempe, AZ (US);

David E. Miner, Chandler, AZ (US);

R. Frank O'Bleness, Tempe, AZ (US);

Steven J. Tu, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.


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